Internal ram upgrade to 640k - continued

[tcat]

Hi All,

I am trying to follow in the discusion of the internal ram upgrade. Just thinking if it were possible to make it external memory upgrade throuh the QL expansion port.

Please see the schema in which I tried to catch the idea of GERTK's design, though I am not sure I understand all details.

QL Ram Expansion Schema

I have these questions:
- GAL's equation, VALID = !A19 * A18 * DS * AS + A19 * !A18 * DS * AS; why is the A19 adress line needed at all, given that SRAM has only A0-A18 address pins?
- GAL's /OE pin I put to GND, to keep it active "L"ow, not sure if correct?
- what value C3 elyt capacitor should be?
- I do not use /ROMCE pin, since I am not replacing system ROMs for síngle EPROM

Please this is my first ever schema I have drawn on PC.
Can anyone help?
Many thanks
TCAT

[tcat]

Hi Brane,

Thank you, I am almost getting there. What troubles me is my lack of understanding of GAL that drives the the addressing logic.

/DTACK and DSMCL are tristate signals and controlled by /OE pin. Address validity is by VALID pin.
At the moment I have /OE put to ground, not sure if that is right.
Shall I connect VALID pin as the input to /OE?

The reference to GERT design is here,
http://theqlforum.com/viewtopic.php?f=2& ... am+upgrade

Many thanks
TCAT

[Dave]

If you think of the memory map as divided into four blocks signaled by A18 and A19. You want the middle two blocks to activate (256K -> 768K) it gets a lot simpler.

A19 A18 Block
..0...0..0K - Block used on BBQL
..0...1..256K - desired mapped in for SRAM
..1...0..512K - desired mapped in for SRAM
..1...1..768K - 128K of this is free, the rest is reserved to map in expansion ROM images

Logically, if we exclusive OR A18 and A19 (0,0 and 1,1 being invalid, 0,1 and 1,0 being valid) we can directly logically indicate when our target block (i.e. device) is being accessed. A 74HCT86 quad 2-input XOR logic could do that with one gate. You could also make an XOR gate by combining gates on a 74HCT00.

You could tie the 512Kx8 SRAM's /OE to +5v, /WE to /RDW and /CS to the inverted output of one gate of 74HCT86, where the two inputs of that gate are fed by A18, A19.

That way you save the complexity and cost of a GAL.

Disclaimer: I haven't had a coffee yet, and it's early here.

[tcat]

Hi Dave,

And thank you for joining in the discussion.
I am no good at h/w, I can see your point, GAL is complex, yet can be programmed so is flexible.

I read in The QL technical guide that add-on card data bus should be a 74LS245 or equivalent, in terms of drive ability, and being tri-state.

Also there are two pins at the expansion port, namely DSMCL and DTACKL, The QL technical guide says, it is necessary for each card to disable the circuitry on the QL itself when that peripheral card recognises its own address. This is achieved by pulling signal DSMCL high before DSL goes low including buffering times. Add-on cards must supply DTACKL or VPAL as required, to notify the CPU that they have recognised their address.

The idea of tristate DSMCL and DTACKL is supported by GERT internal upgrade. I am trying to make it external.

Would you say I can leave this tristate logic out?
Many thanks so far
TCAT

[tcat]

Hi Brane,

Studied the document on timing also read through your reply, THANK YOU.
What the GAL logic does or should do, in my understanding is this,

- when it sees it's own address pull DSMCL high
- set SRAM pins CS,OE,WE accordingly
- wait for SRAM to complete the fetch/store cycle, that is at least 50ns (value taken from specs)
- pull the DSMCL low (tristate high impedance) and confirm the end of cycle by DTACK
- somewhere in between SRAM chip should be dissabled by CS pin

I believe the timing of GAL is also important, and they are actually designed in different speeds.
From 3 to 25ns, the number after the hyphen tells that, e.g.
GALxxVn-25QP is 25ns.
So if GAL is too fast it may not work.
Correct?

Many thanks.
TCAT

[tcat]

Brane,

I believe somewhere in between or after the cycle SRAM chip should also be dissabled by CS pin, to get high impedance on its data pins, correct?

TCAT

[tcat]

Brane,

Thank you so far.
What do you think of theese equations, I have used from GERT example?
I have GAL compiler by V.Bosch (a German lad from Stugardt) for Linux.
Tristate equates are handled by IF statements, so I recoded GERT example as follows,

Code: Select all

GAL20V8
Glue logic for 512x8 SRAM
Sinclair QL RAM Expansion
Based on GERT internal upgrade

SYN = 1
AC0 = 1
AC1(n) = 1,1,1,1,1,1,1,1

#1   2   3     4      5      6      7       8    9     10     11   12
NC   NC  NC    NC     NC     /AS    ROMOEH  /DS  /WR   A18    A19  GND
/OE  NC /RAMCE /RAMOE /RAMWE /ROMCE VALID   NC   DSMCL /DTACK NC   VCC
#13  14 15     16     17     18     19      20   21    22     23   24


  # VALID is active in the memory range $40000-$BFFFF
  VALID = /A19 *  A18 * DS * AS + A19 * /A18 * DS * AS
          
  # ROMCE is inverted ROMOEH
  # IF(OE)
  # ROMCE = ROMOEH
  # GERT used to drive single EPROM internally, I do not need, I guess
           
  # RAMCE is active on memory range $40000-$BFFFF
  IF(OE)
  RAMCE = VALID
       
  # RAMOE is active on read
  IF(OE)
  RAMOE = /WR
 
  # RAMWE is active on write
  IF(OE)
  RAMWE = WR
 
  # DTACK is active on RAM memory range and DS plus AS
  IF(VALID)
  DTACK = OE
     
  # DSMCL disables the internal decoder of QL on our memory range
  IF(VALID)
  DSMCL = OE

ALSO what shall I connect to /OE and VALID pins of GAL?
Do I care about I/CLK pin at all?
This part I am missing completely.

My Schema is here,
http://theqlforum.com/viewtopic.php?f=2&t=890

Thanks so much
TCAT

[tcat]

Brane,

Perfect... I am almost there...
I need to fit +5V voltage regulator since expansion connector provides +9V.
Also GALs come at different speeds, fasters draw more current.

SRAM takes 30mA
GALs depending on model from 55mA to 115mA
Total max of 145mA

I hope it won't need extra heat sink and it won't overheat inside QL.
What do you think?

PLEASE NOTE
I will look at FCx signals this is new information I have not thought of yet. I'd love to update the equates first and come back to you.

Many thanks so far.
TCAT

[tcat]

RAMCS =
DS * A19 * /A18
+ DS * /A19 * A18
+ FC0 * /FC1
+ /FC0 * FC1

Correct?

[1024MAK]

I need to fit +5V voltage regulator since expansion connector provides +9V.

I hope it won't need extra heat sink and it won't overheat inside QL.

Using the +9V supply will not overheat the QL, as this is the supply that comes from the external PSU.
For the relatively simple job that the GAL is doing, and it will not be operating with any really high speed cycles, the current consumption should be at the lower end.
As such, using a 7805 voltage regulator should be okay. Fit it flat to the board and put a large area of copper track around the tab area and you should not need a metal heatsink.

Mark