The Sinclair QL Forum

I was looking for information about an alternative to the 68008 original microprocessor and I've found the 68HC001 as a good replacement.

It can operate with 8 bits buses, addresses 16Mb and there are versions up to 20MHz. Also it's directly compatible with the 68008 bus without glue-logic.

What do you think about it?

The 68SEC000 is a better fit. However, if you change the clock rate you’ll need to generate your own DTACKL as the QL’s is somewhat optimistic. You’ll also need to replace all onboard RAM.

Dave wrote:The 68SEC000 is a better fit. However, if you change the clock rate you’ll need to generate your own DTACKL as the QL’s is somewhat optimistic. You’ll also need to replace all onboard RAM.

So a nice upgrade, the Ram will be faster and in few ICs.. that project... has be done I think, hasn't it?

Dave wrote:The 68SEC000 is a better fit. However, if you change the clock rate you’ll need to generate your own DTACKL as the QL’s is somewhat optimistic. You’ll also need to replace all onboard RAM.

As the 68000 bus is asynchronous, it is enough to obey the /DTACK signal sent by the board to know when the memory cycle is finished. If sufficiently fast RAM were included on the adapter board, /DTACK would be asserted at the same clock cycle where the access starts. I understand for that the factory memory would have to be overridden and the new one would be mapped from $20000 to replace it.

Do you think would this complicate the circuit design too much?

If the original ULA chipset is used, and the CPU is operated at higher speed, there has to be extra circuitry that will fairly faithfully emulate the original 68008 running at 7.5MHz. This is because the 8301 ULA makes certain assumptions about the signal timing on the 68008 in relation to the clock signal, given that the 8301 is also the clock signal generator. Once the CPU clock is not coming from the 8301 those assumptions are not correct and you get RAM read and write errors. If you are reconstructing the entire circuit from scratch, you should not have any problems.
The particular assumption has to do with when write and read data should be present with regards to the DSL signal and DTACKL signal. 68000 derivatives (including 68008, 68HC000, EC000/1 and SEC000 as well as some 68300 series integrated CPUs) latch read data once clock cycle after DTACKL is recognized low so in principle you can pull DTACK low before actual data is available as long as it is available at the appropriate clock edge one cycle later (this is all explained clock edge to clock edge in the relevant datasheets). The 8301 is also the RAM controller and uses this all the time.

Nasta wrote:If the original ULA chipset is used, and the CPU is operated at higher speed, there has to be extra circuitry that will fairly faithfully emulate the original 68008 running at 7.5MHz. This is because the 8301 ULA makes certain assumptions about the signal timing on the 68008 in relation to the clock signal, given that the 8301 is also the clock signal generator. Once the CPU clock is not coming from the 8301 those assumptions are not correct and you get RAM read and write errors. If you are reconstructing the entire circuit from scratch, you should not have any problems.
The particular assumption has to do with when write and read data should be present with regards to the DSL signal and DTACKL signal. 68000 derivatives (including 68008, 68HC000, EC000/1 and SEC000 as well as some 68300 series integrated CPUs) latch read data once clock cycle after DTACKL is recognized low so in principle you can pull DTACK low before actual data is available as long as it is available at the appropriate clock edge one cycle later (this is all explained clock edge to clock edge in the relevant datasheets). The 8301 is also the RAM controller and uses this all the time.

Thank for your advices.

This is the schematic I designed for an adaptor for a 16MHZ version:
https://photos.app.goo.gl/T8opyrJW8pSdVXwAA


This is a pic of a possible (incomplete) layout. It uses a PLLC68 low profile socket:
https://photos.app.goo.gl/c9ePF5Z5SoHFWjJb9

You could simplify this design greatly by tapping into the 15 MHz clock used by the 8301. This means your CPU would be running in step at exactly 2:1 speed, which would give you some simplified timing.

Also, there's not much need to buffer or square the clock, even if you do make your own. You could omit that entirely, whether you generate your own clock or not. A sine wave signal is much less noisy than a more square wave signal.

I woukd just remove the 68008 an try and interface a 68020... oh wait it has been done ... called the Super Gold Card!!!

Derek_Stewart wrote:I woukd just remove the 68008 an try and interface a 68020... oh wait it has been done ... called the Super Gold Card!!!

Super Gold Card is a very expensive and non open piece of hardware and it doesn't support IDE devices.

You can use the 68HC001 as "just a replacement" for the 68008, but it can also be used to expand the RAM beyond 1 Mb. To me, it's ideal in combination with a Qubide interface.

Dave wrote:You could simplify this design greatly by tapping into the 15 MHz clock used by the 8301. This means your CPU would be running in step at exactly 2:1 speed, which would give you some simplified timing.

Also, there's not much need to buffer or square the clock, even if you do make your own. You could omit that entirely, whether you generate your own clock or not. A sine wave signal is much less noisy than a more square wave signal.

I got the clock circuit from the book: "Microprocessor Theory and Applications with 68000/68020 and Pentium". If I can remove the buffer, the new clock generator will be very simple.

Because the design (it uses the 68008 socket). the clock signal is at 7,5MHz, not at 15MHz, so I'd have to double the frequency. Not so simple circuit.