OPD: Computer One floppy interface recreation.

[stephen_usher]

Built the first one and it doesn't work. I think that I have the address decode logic wrong in the GAL.

This is the original logic (on the schematic):

And this is my GAL code:

Code: Select all

Name     OPD Computer One Floppy Interface Address Decode ;
PartNo   00 ;
Date     7/7/2024 ;
Revision 02 ;
Designer Engineer ;
Company  Personal ;
Assembly None ;
Location  ;
Device   g16v8 ;

/* *************** INPUT PINS *********************/
PIN  1 = !OE; /**/ 
PIN  2 = !CE; /**/ 
PIN  3 = A13; /**/ 
PIN  4 = A14; /**/ 
PIN  5 = RW; /**/ 
PIN  6 = DEN; /**/ 
/*PIN  7 = NC; /**/ 
/*PIN  8 = NC; /**/
/*PIN  9 = NC; /**/
/*PIN 11 = NC; /**/

/* *************** OUTPUT PINS *********************/
/*PIN 12 = ; /**/
/*PIN 13 = ; /**/
/*PIN 14 = ; /**/
/*PIN 15 = ; /**/
/*PIN 16 = ; /**/
PIN 17 = !1772CS; /**/
PIN 18 = !175CP; /**/
PIN 19 = !ROMOE; /**/

ENABLE = OE # CE;

A13N14 = A13 & !A14;

1772CS = ENABLE & A14 & A13;

175CP = ENABLE & A13N14 & !RW;

ROMOE = ENABLE & RW & !A14;

Can anyone see the bad logic, especially when it comes to the 1772 as that seems to be accessed erroneously almost constantly.

[Pr0f]

I am wondering if relying on the input / output labels to do the negation is not working.

FDC select is active only when DSL (OE) is low, and CE is low (capsule selected) and A14 and A13 are both high

What logic compiler are you using?

[stephen_usher]

P.S. The ENABLE was wrong, should have been OE & CE. At least the WD1772 isn't being constantly accessed... it's not being accessed at all now.

Definitely got the logic wrong somewhere else.

[stephen_usher]

I am wondering if relying on the input / output labels to do the negation is not working.

FDC select is active only when DSL (OE) is low, and CE is low (capsule selected) and A14 and A13 are both high

What logic compiler are you using?

WinCUPL

[stephen_usher]

I think I've been confused by the NOR gates, I have the addressing of the latch incorrect, I had it as A13 & !A14 and it should be the opposite way around.

[stephen_usher]

Yay! Done! Working!

[Pr0f]

Did you not fancy putting the latch into the GAL as well? You have spare pins, but you would need to free up pin 1 as a clock input, feed it from the select output for the 175 latch, and WinCUPL should select combinatorial mode, as you have both registered and non registered logic then.

[Pr0f]

Yay! Done! Working!

Nice one - Always good when you get a win

[stephen_usher]

Did you not fancy putting the latch into the GAL as well? You have spare pins, but you would need to free up pin 1 as a clock input, feed it from the select output for the 175 latch, and WinCUPL should select combinatorial mode, as you have both registered and non registered logic then.

Not really... I believe in KISS... Do as few changes as possible in each iteration. In this case simplifying the address select logic.

[stephen_usher]

Everything checks out OK.

So, here's the "Version 1.0" schematic: