Hi From London England

[Pr0f]

One thing to bear in mind - the 2 sockets are effecitvely wired in parallel, so you can't just put 2 x 32K EPROM in them, one in each socket. There are a bunch of jumper resistors and a place for an IC (if you have an older model board - issue 5) that will allow selection of different memory layouts - I think this is documented in the service manual - which will be on Dilwyns excellent site (www.dilwyn.me.uk).

From memory valid combo's are :

3 x 16K (2 are piggy back with a flying lead)
1 x 32K and 1 x 16K

The original ROM chips were a 32K and a 16K and they can be wired in parallel as one has a positive chip enable and one a negated chip enable on the same pin, meaning that one of the address lines (A15) will select which ROM to use.

[Ruptor]

The original ROM chips were a 32K and a 16K and they can be wired in parallel as one has a positive chip enable and one a negated chip enable on the same pin, meaning that one of the address lines (A15) will select which ROM to use.

Thanks Pr0f. Nothing is simple is it? My intention was to up grade to Tychie that is 64K hence using two 32K ROMs if I can fix my QL because I don't want to use external ROMs and the memory is contiguous as if Tychie was meant for the 64K. The base sticker is yellow reading A5..1 so I assume I have a modified issue 5 board but I can't see IC17 that is shown with dotted lines on the issue 5 schematic. It is difficult to see on the scanned circuit what is going on with the pin 22 decoding but the manual says the ROMOEH signal selects the ROMs so isn't just a case of using the A15 line to enable one of the ROM outputs then I could use two 32K chips? The 32K chips are M27C256B and have output enable and chip select pins. Can anyone point me to legible schematics of issue 5 & 6?

[Pr0f]

Again - Dilwyns site has the circuit diagrams for issue 5 and issue 6, but the issue 5 is 'cleaned up' and removes the dotted line information showing the rom option links and the missing IC that decodes them.

I've had a look at that diagram and the top most gate of that ic - pin 8 output goes to 'x' - this is a NAND output of ROMOEH and A15 - which could be used to provide a CS signal to the upper ROM of a 2 x 32K set of ROMS, but you'd need a flying wire from pin 22 to that 'X' point - not sure if that was a test point or empty solder pad or just nothing on the board - I will have to go check my issue 5 board and have a look - if you did that, then you'd need to fit that 4 x 2 Input NAND chip 74LS00.

JU2 must be fitted to feed A14 to pin 27 of both ROM chip sockets - as that's needed for the Eprom chips, but it looks like fitting the NAND chips would interfere with the other ROM Select signals. I've scanned the circuit around IC17

[Ruptor]

Thanks for looking. This is where I am now. The ROMOEH signal goes directly to pin 22 on both ROM sockets therefore the board is an issue 6 and this makes it easy I think although I might be wrong. The old 16K ROM must be the one that inverts its input because the A15 signal is used to enable the 32K chip when zero and enable the 16K when one.
Oh! my initial thought is wrong thinking I could just swap the ROMOEH & A15 on one chip because although the logic is right one is a physical output enable and it would stuff the bus on every A15 low signal. The solution is to invert the A15 line for the 16K slot but my board doesn't have an IC17 so if there are no spare gates perhaps I could use an FET to invert the signal. One transistor and a couple of or maybe just one resistor is easier to fit than a TTL chip. Some more thought required to use two 32K chips but I could use one in the lower slot without mods I think I just need to put the JM code in it not the JS as is.

[Pr0f]

Pin 22 is your OE signal, which is LOW to select the ROM Output to the databus, but the signal from the QL is a high one - as in it is active High - a standard Eprom will be selected only when it should not be.

For the Eproms to work - you need to do something like the following:

Invert the ROMOEH signal and use it to operate pin 22 on both ROMS

Use A15 to act as CS on pin 20 (active Low) for the lower EPROM (0000-7FFF) and use an inverted copy of A15 to act as CS for the upper EPROM (8000-FFFF)

any inverting gate logic chip that has normal (not open collector) output, should work for both signals - just tie the inputs together for each gate - 2 ready made inverters, you will need to bend out the pin 22 of each EPROM for it's inverted chip select, and pin 20 on the upper EPROM - it doesn't matter which socket you use for either chip, as they are just wired in parallel.

[Ruptor]

Pin 22 is your OE signal, which is LOW to select the ROM Output to the databus, but the signal from the QL is a high one - as in it is active High - a standard Eprom will be selected only when it should not be.

Something is wrong if you look at the pinouts of the picture on the seventh post down on the previous page. First I need to know the correct signal orientation then I can figure it out. According to you the chip picture is wrong but I have seen the same for the 23256 elsewhere.
Does this have a novel way of inverting enable signals or does it mean the 23 and 27 series have the same polarity logic signals?
http://vic-20.de/x1541/hardware/2364.html

[Pr0f]

chips with 23xxx are ROM chips - the ones Sinclair used had both low and high chip selects, which is why they can be wired piggy back or placed in the two ROM sockets as the will never both be selected at the same time

Take a look at this datasheet for the 23256 - the CS and OE outputs are polarity programmable, so can be active high or active low - the vendor can chose which he needs before the chip is masked. The Eprom 27256 is as far as I know only available for active low on both CS and OE pins (20 and 22), so will not function as a direct replacement without some logic help.

https://datasheetspdf.com/pdf/1093091/UMC/UM23256/1

The Minvera boards use a 27512 chip, but have a small logic chip on the board to provide the necessary logic levels to work.

[Ruptor]

Thanks I searched and couldn't find a datasheet like that only ones where the enables were fixed. So all I have to do is invert the ROMOEH > ROMOEL signal to match the 27C256 because the A15 already selects the upper or lower chip. It just means I have to swap the upper and lower chips in the sockets for the 27C256.

[Pr0f]

The A15 will still select both 27c256 - as the sockets are wired exactly the same - so you need to innvert the A15 for one of the chips and that one will carry the upper ROM portion of code.

[Ruptor]

The A15 will still select both 27c256 - as the sockets are wired exactly the same - so you need to innvert the A15 for one of the chips and that one will carry the upper ROM portion of code.

Yes sorry for being so thick I just couldn't get my brain to accept that the original ROMs would have different pin programming but the penny dropped last night. So final scheme is use one 64K & invert ROMOEH. Of course I don't have any 64K EPROMs. I could write some test code and use one EPROM in zero I suppose to get the board running. Thanks for the help. Is there any code lying around that fits a 32K chip?