The Sinclair QL Forum

And here's the promised video with the QL repairs (double feature!):


Edit: I can't see the embedded version. Weird. https://youtu.be/0z4X4AMKlcs

llopis wrote:And here's the promised video with the QL repairs (double feature!):


Edit: I can't see the embedded version. Weird. https://youtu.be/0z4X4AMKlcs

Excelent Noel!

I already commented on the video, but again, sooo cool to see such a professionally done video about the QL, thank you!

Though I do prefer my style of Minerva adapter (quick & so dirty I'm hesitant to post pictures )

Looks good enough to me

Hi,

This is basically the way the Qview Minerva ro board works, I was going to use a SMD 74HCT04 chip and make the PCB routed so that the three legs from the EEPROM are not separate from the socket.

But like most things these days, still in design stage.

Derek_Stewart wrote:Hi,

This is basically the way the Qview Minerva ro board works, I was going to use a SMD 74HCT04 chip and make the PCB routed so that the three legs from the EEPROM are not separate from the socket.

Umm, how is that supposed to work? The legs cannot be connected to the QL board, so either you use two separate row of pins like in the video or you bend the three pins.

Marcel

mk79 wrote:I already commented on the video, but again, sooo cool to see such a professionally done video about the QL, thank you!

Though I do prefer my style of Minerva adapter (quick & so dirty I'm hesitant to post pictures )
Minerva_Adapter1.jpgMinerva_Adapter2.jpgMinerva_Adapter3.jpg

Hehe done many this way - but I d have a small complaint - unused inputs of HC/HCT or indeed any CMOS family logic chips should be tied to a fixed logic potential, not left floating. Unlike regular TTL and derived families, which kind of default to high, CMOS is really floating in a VERY high impedance state so all sorts of electromagnetic garbage can influence them resulting in unused gates processing fake signals, increasing power drain and regenerating said EM garbage. Unfortunately, there is one more peril. Most regular CMOS chips do not like to have their inputs stuck logically 'neither here or there' - somewhere in the middle between logic 0 and 1. They are designed for this state to tast extremely short (during signal transitions) because in some cases it will result in the output of the chip simultaneously trying to pull high or low - in other words, it will pass current between it's power supply and ground, sometimes far more than it's designed for. In some cases, it will oscillate at a very high frequency (often hundreds of MHz!) around the midpoint of the power supply voltage while it's doing the 'power supply shorting' thing, making it all even worse. The only sure exception to this are inputs with a Schmit trigger capability, but these do not happen often (HC(T)14, HC(T)132 and some buffers).

Nasta wrote:Hehe done many this way - but I d have a small complaint

I just did it this way to draw you out of the woods No, you're totally right, my only excuse is that this was a 5-minute hack-job that was just used for testing something quickly. Normally my QLs are equipped with QL-SDs anyway
The only problem with this kind of adapter is to find socket strips with long enough leads. For QL-SD and the board here I used Preci-dip 311-87-164-41-001101, which are fine, but there are also MPE-GARRY 006-1-032-D-B3STF-XS0, which are even longer but harder to source (plus I already had ordered a life supply of Preci-dip when I found the MPE Garry). Happy now?

Nice to hear from you Nasta!

Nasta wrote:...unused inputs of HC/HCT or indeed any CMOS family logic chips should be tied to a fixed logic potential, not left floating.

I've sometimes wondered whether tying those unused CMOS inputs high orlow is preferred, or does the choice not matter? Is a direct connection to the relevant powerline preferred over using a pull-up/down resistor?

And unused outputs - can they be left unconnected?

tie up or down is fine - and outputs can be left to swing which ever way they will go, based on logic function.