Nasta wrote: Mon Apr 29, 2024 9:49 pm
So, a hat's off Peter, this is the best QL hardware idea I have seen in a really long time!
Many thanks Nasta. It is debatable whether a card for the expansion slot would have been a better idea.
Doing it in an unorthodox way was more fun though.
Nasta wrote: Mon Apr 29, 2024 9:49 pm
I never thought of doing it the 'other way' but did briefly think of something similar back in the day while developing the ill fated GoldFire but back then CPLDs were just a dream and it would not fit efficiently into a CPLD, so I quickly discarded the idea.
It is sad that you didn't finish the GoldFire. The 68EC040-like CPU with multiplexed bus was really cool at the time. A few years ago, I had the chance to get the CPU in new condition for low cost and was quite tempted. But in the end, the 68060 is probably the better way to go when it comes to a "high end" QL compatible.
Nasta wrote: Mon Apr 29, 2024 9:49 pm
Back to the two extra pins, might I offer a suggestion?
The extra pins are not used yet, so I'm open for whatever ideas you have. It is easily possible to solder a 2.54 mm pin dual row header to the QIMSI Gold pads and plug it onto a different PCB. The extra pins just allow a bit more flexibility.
Nasta wrote: Mon Apr 29, 2024 9:49 pm
Instead of the R/W pin there should be a 'rom write'. An undecoded R/W is not much help as it does not qualify the data with a data strobe, but decoding a write signal for the ROM space, now we are cooking.
That is a nice possibility. Of course it only makes sense together with a second board generating that signal, which brings up the question what the goal of that board would be.
Nasta wrote: Mon Apr 29, 2024 9:49 pm
The idea behind this would be to provide faster access to the communications FIFO to the CPU on the QIMSI Gold, because the QL side is quite slow at bit-banging.
Another possibility would be to use an atomic CPU access that has a data bus write immediately following a read, e.g. an OR.B Dx,(Ax) instruction. The FPGA would see the read access and know that the write data will follow after a known delay, when it can sample. That would already work with the traditional ROM port.
Nasta wrote: Mon Apr 29, 2024 9:49 pm
Oh, BTW is the 'detect' pin an input?
Yes, with pullup. It is not actually used yet, but the idea was to see if QIMSI Gold is plugged into "something else" and then provide "something else" on all the other pins.
Nasta wrote: Mon Apr 29, 2024 9:49 pm
So, someone could do a really small board with a really cut down QL. If no video is needed, some RAM, CPLD that would emulate the basics of the 8302 (the clock, the interrupts and the IPC access), and the IPC (with keyboard inputs). In theory even less is required if a different ROM is provided or even better if the QIMSI side provides some boot code)...
If you have something specific in mind, I'm willing to adapt to your requirements, time permitting.
The Qzero might also be an option. It has more hardware resources and I/O.
Or we revive the "N68" idea. I have seen the the ECP5 is now available in a TQFP-144 case.
Hope we can talk at Dormagen.
